A design tool simplifies the process of specifying the design of an electronic circuit or system. With a design tool, a designer specifies the design in a way that abstracts away certain timing and structural details. The design tool then transforms the higher-level specification into a lower-level specification that is closer to an actual hardware implementation. The design tool shields the designer from many of the complexities of the design, making the design process faster and more cost effective.
Different design tools provide different ways for a designer to specify a design. Some design tools accept textual specifications from the designer; other design tools accept graphical specifications. While some design tools accept high-level, abstract specifications of design behavior, other design tools require low-level specifications with hardware details.
A behavioral synthesis tool is one kind of design tool. With a behavioral synthesis tool, the designer specifies a design by describing the behavior of the design. Many behavioral synthesis tools work with a hardware description language [“HDL”] such as VHDL or VERILOG®. For additional information about electronic design automation, behavioral synthesis tools, and HDLs, see John P. Elliott, Understanding Behavioral Synthesis, Kluwer Academic Publishers (1999).
FIG. 1 shows a VHDL listing (100) for a simple design with nested loops. After standard code that defines support libraries, an interface, and local variables, the VHDL listing (100) includes a main body with several nested loops. The main body includes a main loop (110) enclosing a WHILE loop (120). The WHILE loop (120) in turn encloses first and second FOR loops (130, 140). Although the VHDL listing (100) is fairly simple, a VHDL listing for a real-world application can contain hundreds or thousands of lines of code.
A good design tool provides the designer with accurate and helpful information about the design. For different stages in the design process, design tools use different techniques to present information about the design. For example, many design tools use a Gantt chart to present the results of scheduling the design process. In scheduling, a design tool assigns the operations of the design to steps timed by a clock.
FIGS. 2a–2c show a Gantt chart (200) presenting a design schedule for the design of FIG. 1. The top row (205) of the Gantt chart (200) includes labels for control steps [“c-steps”] 1–5 of the design schedule. The c-steps partition the operations of the design schedule into clock cycles, where each c-step includes scheduled operations that are performed in a clock cycle. The design schedule begins at c-step 1 and proceeds to the right. The leftmost column (210) of the Gantt chart (200) lists labels for the scheduled operations of the design. The numbers in the labels relate to line numbers in the design specification.
To show the design schedule at different levels, the Gantt chart (200) expands or collapses presentation of scheduling information for loops. In FIG. 2a, for example, the Gantt chart (200) presents the design schedule and list of scheduled operations for the main loop (110), but hides that information for the nested loops (120, 130, 140). In FIGS. 2b and 2c, the Gantt chart (200) adds design schedule details and lists scheduled operations for the WHILE loop (120) and the FOR loops (130, 140) respectively.
When the Gantt chart (200) hides scheduling information for a loop, the leftmost column (210) summarizes operations within the loop using a LOOP operation label. The loop is graphically presented as a rectangular outline in the design schedule of the enclosing loop. The outline extends for the number of clock cycles taken by one iteration of the nested loop. Thus, FIG. 2a includes a rectangular outline (220) representing the WHILE loop (120), and FIGS. 2b and 2c include rectangular outlines (230, 240) representing the FOR loops (130, 140).
Within the Gantt chart (200), each of the listed scheduled operations is represented with a rectangular icon. The width of the rectangular icon roughly indicates the actual delay of the operation. For example, a multiplication operation takes longer than a comparison operation, so the icon for a MUL operation is wider than the icon for a LESSTHAN operation.
Although the Gantt chart (200) helps a designer understand a design schedule, the Gantt chart (200) has several shortcomings with respect to the presentation of nested loops.
With reference to FIGS. 1 and 2a–2c, the c-step numbering in the Gantt chart (200) does not accurately illustrate the actual timing of execution of the nested loops. For example, in FIGS. 2a–2c, c-step 5 of the main loop does not execute four clock cycles after c-step 1, but rather executes an indeterminate number of clock cycles after c-step 1 due to the nested loops (120, 130, 140). As another example, suppose min1 is greater than min2 at the start. The WHILE loop (120) and FOR loops (130, 140) never execute, and c-step 5 does not execute four clock cycles after c-step 1. Using the c-step numbers of the main loop for nested loops is misleading in several respects.
Aside from c-step numbering, the presentation of nested loops in the Gantt chart (200) may not correctly illustrate actual scheduling. With some design tools, a nested loop is scheduled separately from its enclosing loop, potentially under different constraints. Thus, presenting a nested loop in the same timing and scheduling context as its enclosing loop can be misleading.
Further, the list of scheduled operations in the Gantt chart (200) obscures the nesting relationships between loops. The list does not clearly indicate which operations are for which loops, or whether a loop is expanded or collapsed.
Finally, the rectangular icons for scheduled operations do not accurately represent actual delay for many types of scheduled operations. For a scheduled operation with a short delay or no real delay, the icon has a minimum, visible width which does not accurately represent actual delay. Moreover, none of the icons is marked or otherwise distinguished from other icons, making it harder for the designer to associate icons with scheduled operations.